EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 71

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clocking Modes
Altera Corporation-Preliminary
March 2007
Clocking Mode
Independent
Input/output
Read/write
Single-clock
Table 4–6. Cyclone III Memory Clock Modes
f
True Dual-Port Mode
v
v
v
ROM Mode
Cyclone III memory blocks support ROM mode. A memory initialization
file (.mif) initializes the ROM contents of these blocks. The address lines
of the ROM are registered. The outputs can be registered or unregistered.
The ROM read operation is identical to the read operation in the single-
port RAM configuration.
FIFO Buffer Mode
Cyclone III memory blocks support single clock or dual clock FIFO buffer.
Dual clock FIFO buffers are useful when transferring data from one clock
domain to another clock domain. Cyclone III memory blocks do not
support simultaneous read and write from an empty FIFO buffer.
Refer to the Single- and Dual-Clock FIFO Megafunctions User Guide for
more information on FIFO buffers. You will find this at the Altera web
site at http://www.altera.com/literature/ug/ug_fifo.pdf.
Cyclone III M9K memory blocks support the following clocking modes:
■
■
■
■
1
1
Table 4–6
Independent
Input/output
Read/write
Single-clock
Violating the setup or hold time on the memory block input
registers could corrupt the memory contents. This applies to
both read and write operations.
Asynchronous clears are available on read address registers,
output registers and output latches only.
shows the clocking mode versus memory mode support matrix.
Simple Dual-Port Mode Single-Port Mode
v
v
v
Cyclone III Device Handbook, Volume 1
v
v
ROM Mode
Clocking Modes
v
v
v
FIFO Mode
4–17
v
v