EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 137

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

PLL
Reconfiguration
Altera Corporation-Preliminary
March 2007
PLLs use several divide counters and different VCO phase taps to
perform frequency synthesis and phase shifts. In Cyclone III PLLs, you
can reconfigure both the counter settings and phase shift the PLL output
clock in real time. You can also change the charge pump and loop filter
components, which dynamically affects the PLL bandwidth. You can use
these PLL components to update the output clock frequency, PLL
bandwidth, and phase-shift in real time, without reconfiguring the entire
FPGA.
The ability to reconfigure the PLL in real time is useful in applications that
might operate at multiple frequencies. It is also useful in prototyping
environments, allowing you to sweep PLL output frequencies and adjust
the output clock phase dynamically. For instance, a system generating
test patterns is required to generate and transmit patterns at 75 or
150 MHz, depending on the requirements of the device under test.
Reconfiguring the PLL components in real time allows you to switch
between two such output frequencies within a few microseconds.
You can also use this feature to adjust clock-to-out (tco) delays in real time
by changing the PLL output clock phase shift. This approach eliminates
the need to regenerate a configuration file with the new PLL settings.
PLL Reconfiguration Hardware Implementation
The following PLL components are configurable in real time.
■
■
■
■
Figure 6–22
shifting their new settings into a serial shift register chain or scan chain.
Serial data shifts to the scan chain via the scandataport and shift
registers are clocked by scanclk. The maximum scanclk frequency is
100 MHz. After shifting the last bit of data, asserting the configupdate
signal for at least one scanclk clock cycle synchronously updates the
PLL configuration bits with the data in the scan registers.
Pre-scale counter (n)
Feedback counter (m)
Post-scale output counters (c0-c4)
Dynamically adjust the charge pump current (I
components (R, C) to facilitate on the fly reconfiguration of the PLL
bandwidth.
shows how to dynamically adjust PLL counter settings, by
Cyclone III Device Handbook, Volume 1
cp
PLL Reconfiguration
), loop filter
6–37