EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 59

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
(enabled), in which case writing is controlled only by the write-enable
signals. There is no clear port to the byte-enable registers. M9K blocks
support byte enables when the write port has a data width of ×16, ×18,
×32, or ×36 bits.
Byte enables operate in one-hot manner, with the least significant bit
(LSB) of the byteena signal corresponding to the least significant byte of
the data bus. For example, if using a RAM block in ×18 mode, with
byteena = 01, data[8..0] is enabled and data[17..9] is disabled.
Similarly, if byteena = 11, both data[8..0] and data[17..9] are
enabled. Byte enables are active high.
selection.
Note to
(1)
Table 4–3. Byte Enable for Cyclone III M9K Blocks
byteena[3..0]
Any combination of byte enables is possible.
[0] = 1
[1] = 1
[2] = 1
[3] = 1
Table
4–3:
datain×16
[15..8]
[7..0]
-
-
datain×18
[17..9]
Cyclone III Device Handbook, Volume 1
[8..0]
-
-
Affected Bytes
Table 4–3
datain×32
summarizes the byte
(1)
[23..16]
[31..24]
[15..8]
[7..0]
datain×36
[26..18]
[35..27]
[17..9]
[8..0]
Overview
4–5