EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 116

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
Cyclone III PLL
6–16
Cyclone III Device Handbook, Volume 1
Cyclone III PLL Hardware Overview
Cyclone III devices contain up to four PLLs with advanced clock
management features. The main goal of a PLL is to synchronize the phase
and frequency of an internal or external clock to an input reference clock.
There are a number of components that comprise a PLL to achieve this
phase alignment.
Cyclone III PLLs align the rising edge of the input reference clock to a
feedback clock using the phase-frequency detector (PFD). The duty-cycle
specifications determine the falling edges. The PFD produces an up or
down signal that determines whether the voltage-controlled oscillator
(VCO) needs to operate at a higher or lower frequency. The output of the
PFD feeds the charge pump and loop filter, which produces a control
voltage for setting the VCO frequency. If the PFD produces an up signal,
then the VCO frequency increases. A down signal decreases the VCO
frequency. The PFD generates these up and down signals to a charge
pump. If the charge pump receives an up signal, it drives current into the
loop filter. Conversely, if it receives a down signal, it draws current from
the loop filter.
The loop filter converts these up and down signals to a voltage used to bias
the VCO. The loop filter also removes glitches from the charge pump and
prevents voltage over-shoot, which filters the jitter on the VCO. The
voltage from the loop filter determines how fast the VCO operates. A
divide counter (m) is inserted in the feedback loop to increase the VCO
frequency above the input reference clock. VCO frequency (f
to (m) times the input reference clock (f
(f
counter. Therefore, the feedback clock (f
PFD is locked to the f
The VCO output from the PLLs can feed five post-scale counters
(C[4..0]). These post-scale counters allow the PLL to produce a number
of harmonically related frequencies.
REF
) to the PFD is equal to the input clock (f
REF
that is applied to the other input of the PFD.
REF
FB
) applied to one input of the
). The input reference clock
Altera Corporation- Preliminary
IN
) divided by the pre-scale
VCO
March 2007
) is equal