EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 290

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Configuring Cyclone III Devices
Figure 10–17. PS Configuration Timing Waveform
Notes to
(1)
(2)
(3)
(4)
(5)
10–54
Cyclone III Device Handbook, Volume 1
t
t
t
t
t
t
t
t
C F 2 C D
C F 2 S T 0
C F G
S TAT U S
C F 2 S T 1
C F 2 C K
S T 2 C K
D S U
Table 10–11. PS Timing Parameters for Cyclone III Devices (Part 1 of 2)
Symbol
The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS and CONF_DONE
are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
Upon power-up, the Cyclone III device holds nSTATUS low for the time of the POR delay.
Upon power-up, before and during configuration, CONF_DONE is low.
In user mode, drive DCLK either high or low when using the PS configuration scheme, whichever is more
convenient. When using the AS configuration scheme, DCLK is a Cyclone III output pin and should not be driven
externally.
Do not leave the DATA[0] pin floating after configuration. Drive it high or low, whichever is more convenient.
Figure
CONF_DONE (3)
nSTATUS (2)
INIT_DONE
nCONFIG
DCLK (4)
10–17:
nCONFIG
nCONFIG
nCONFIG
nSTATUS
nCONFIG
nCONFIG
nSTATUS
Data setup time before rising edge on
User I/O
DATA[0]
Tri-stated with internal pull-up resistor
low to
low to
low pulse width
low pulse width
high to
high to first rising edge on
high to first rising edge of
t
t
CFG
CF2CD
t
Table 10–11
configuration.
CF2ST1
t
CF2ST0
t
Parameter
CONF_DONE
nSTATUS
CF2CK
t
ST2CK
nSTATUS
t
Bit 0 Bit 1 Bit 2 Bit 3
STATUS
t
CH
t
CLK
t
DSU
t
CL
t
DH
defines the timing parameters for Cyclone III devices for PS
low
high
low
DCLK
DCLK
DCLK
Note (1)
Bit n
Minimum
230
230
500
70
5
(2)
(2)
Altera Corporation-Preliminary
t
CD2UM
Note (1)
Maximu
230
230
User Mode
500
500
(5)
m
(2)
(2)
March 2007
Units
ns
ns
ns
ns
µs
µs
µs
µs