EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 170

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device I/O Features
Figure 7–9. Cyclone III On-Chip Series Termination Without Calibration
7–18
Cyclone III Device Handbook, Volume 1
50 Ω) for SSTL-2 and SSTL-18. Figure shows the single-ended I/O
standards for on-chip termination without calibration. The R
the intrinsic transistor impedance.
All I/O banks and I/O pins support impedance matching and series
termination. Dedicated configuration pins and JTAG pins do not support
impedance matching or series termination.
standards that support impedance matching the series termination.
Series Impedance
3.0-V LVTTL
3.0-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
Cyclone III Driver
Table 7–4. Selectable I/O Drivers for On-Chip Termination without
Calibration (Part 1 of 2)
I/O Standard
V
GND
CCIO
R
R
S
S
On Chip Series Termination without Calibration
Row I/O
Z
O
50
25
50
25
50
25
50
25
Receiving
Device
Column I/O
Altera Corporation-Preliminary
Table 7–4
Setting
50
25
50
25
50
25
50
25
p
lists the I/O
S
March 2007
shown is
Unit
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω