EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 111

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Altera Corporation-Preliminary
March 2007
f
When a clock network is disabled, all the logic fed by the clock network
is in an off-state, thereby reducing the overall power consumption of the
device. This function is independent of the PLL and is applied directly on
the clock network, as shown in
sources and the clkena signals for the global clock network multiplexers
can be set through the Quartus II software using the altclkctrl
megafunction.
Refer to the altclkctrl Megafunction User Guide for
more information.
Clkena Signals
In Cyclone III, devices support clkena signals at the clock network level.
Figure 6–5
the clock even when a PLL is used. Upon re-enabling the output clock, the
PLL does not need a resynchronization or re-lock period because the
circuit gates off the clock at the clock network level. In addition, the PLL
can remain locked independent of the clkena signals since the loop-
related counters are not affected.
Figure 6–5. Clkena Implementation
shows how to implement clkena. This allows you to gate off
clkena
clkin
Figure 6–1 on page
D
Cyclone III Device Handbook, Volume 1
Q
clkena_out
6–7. The input clock
clk_out
Clock Networks
6–11