EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 102
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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4–30
Table 4–9. DSP Block Dynamic Signals for DSP Block in Arria II Devices (Part 1 of 2)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DSP Block Dynamic Signals per Half-DSP Block
signa
signb
output_round
chainout_round
output_saturate
chainout_saturate
accum_sload
zero_chainout
zero_loopback
rotate
Signal Name
DSP Block Control Signals
If both the rounding and saturation logic units are used for an accumulation type of
operation, the format is:
Result = SAT[RND[
You can configure the Arria II DSP block with a set of static and dynamic signals. At
run time, you can configure the DSP block dynamic signals to toggle or not.
Table 4–9
block dynamic signals.
Signed/unsigned control for all multipliers and adders.
signa for “multiplicand” input bus to dataa[17:0] each multiplier.
signb for “multiplier” input bus datab[17:0] to each multiplier.
■
■
■
■
Round control for first stage round/saturation block.
■
■
Round control for second stage round/saturation block.
■
■
Saturation control for first stage round/saturation block for Q-format
multiply. If both rounding and saturation is enabled, saturation is done
on the rounded result.
■
■
Saturation control for second stage round/saturation block for
Q-format multiply. If both rounding and saturation is enabled,
saturation is done on the rounded result.
■
■
Dynamically specifies whether the accumulator value is zero.
■
■
Dynamically specifies whether the chainout value is zero.
Dynamically specifies whether the loopback value is zero.
rotation = 1, rotation feature is enabled
shows a list of dynamic signals for the DSP block.
signa = 1, signb = 1 for signed-signed multiplication
signa = 1, signb = 0 for signed-unsigned multiplication
signa = 0, signb = 1 for unsigned-signed multiplication
signa = 0, signb = 0 for unsigned-unsigned multiplication
output_round = 1 for rounding on multiply output
output_round = 0 for normal multiply output
chainout_round = 1 for rounding on multiply output
chainout_round = 0 for normal multiply output
output_saturate = 1 for saturation support
output_saturate = 0 for no saturation support
chainout_saturate = 1 for saturation support
chainout_saturate = 0 for no saturation support
accum_sload = 0, accumulation input is from the output registers
accum_sload = 1, accumulation input is set to be zero
∑
(A × B)]]
Function
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
December 2010 Altera Corporation
Table 4–9
lists the DSP
Count
2
1
1
1
1
1
1
1
1
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