EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 60
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Quantity
Price
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Part Number:
EP2AGX45DF29I5N
Manufacturer:
ALTERA
Quantity:
201
Company:
Part Number:
EP2AGX45DF29I5N
Manufacturer:
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Quantity:
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- EP2AGX45CU17C6N PDF datasheet
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3–14
Figure 3–13. Simple Dual-Port Timing Waveforms for M9K and M144K Blocks
Figure 3–14. Simple Dual-Port Timing Waveforms for MLABs
Arria II Device Handbook Volume 1: Device Interfaces and Integration
q (asynch)
q (asynch)
wraddress
wraddress
rdaddress
rdaddress
wrclock
rdclock
wrclock
rdclock
wren
data
rden
data
rden
wren
din-1
doutn-1
Figure 3–13
dual-port mode with unregistered outputs for M9K and M144K blocks. Registering
the M9K and M144K block outputs delay the q output by one clock cycle.
an-1
Figure 3–14
dual-port mode with unregistered outputs in the MLAB. The write operation is
triggered by the falling clock edges.
din-1
doutn-1
an-1
bn
bn
an
an
din
din
shows timing waveforms for read and write operations in simple
shows the timing waveforms for read and write operations in simple
doutn
doutn
b0
a0
a0
b0
a1
a1
dout0
dout0
a2
b1
a2
b1
a3
a3
Chapter 3: Memory Blocks in Arria II Devices
din4
din4
a4
b2
a4
b2
December 2010 Altera Corporation
din5
a5
din5
a5
b3
b3
din6
a6
din6
a6
Memory Modes
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