EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 464
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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1–78
Arria II Device Handbook Volume 2: Transceivers
1
Unlike Ethernet, where the LSB of the parallel data byte is transferred first,
SONET/SDH requires the MSB to be transferred first. To facilitate the MSB-to-LSB
transfer, you must enable the Flip Transmitter input data bits and Flip Receiver
output data bits options in the ALTGX MegaWizard Plug-In Manager.
Depending on whether data bytes are transferred MSB-to-LSB or LSB-to-MSB, you
must select the appropriate word aligner settings in the ALTGX MegaWizard Plug-In
Manager.
Word Aligner in SONET/SDH Mode
The word aligner in SONET/SDH functional mode is configured in manual
alignment mode. You can configure the word aligner to either align to a 16-bit A1A2
pattern or a 32-bit A1A1A2A2 pattern, controlled by the rx_a1a2size input port to the
transceiver.
A low level on the rx_a1a2size port configures the word aligner to align to a 16-bit
A1A2 pattern; a high level configures the word aligner to align to a 32-bit A1A1A2A2
pattern.
In OC-96 configurations, the word aligner is only allowed to align to an A1A1A2A2
pattern, so the input port rx_ala2size is unavailable. Barring this difference, the
OC-96 word alignment operation is similar to that of the OC-12 and OC-48
configurations.
You can also configure the word aligner to flip the word alignment pattern bits
programmed in the ALTGX MegaWizard Plug-In Manager and compare them with
the incoming data for alignment. This feature offers flexibility to the SONET
backplane system for either a MSB-to-LSB or LSB-to-MSB data transfer.
lists word alignment patterns that you must program in the ALTGX MegaWizard
Plug-In Manager based on the bit-transmission order and the word aligner bit-flip
option.
Table 1–21. Word Aligner Settings for Arria II Devices
OC-48 and OC-96 Byte Serializer and Deserializer
The OC-48 and OC-96 transceiver datapath includes the byte serializer and
deserializer to allow the PLD interface to run at a lower speed. The OC-12
configuration does not use the byte serializer and deserializer blocks. The byte
serializer and deserializer blocks are explained in
“Byte Deserializer” on page
The OC-48 byte serializer converts 16-bit data words from the FPGA fabric and
translates the 16-bit data words into two 8-bit data bytes at twice the rate. The OC-48
byte deserializer takes in two consecutive 8-bit data bytes and translates them into a
16-bit data word to the FPGA fabric at half the rate.
Serial Bit Transmission Order
MSB-to-LSB
MSB-to-LSB
LSB-to-MSB
1–43, respectively.
Flip the Word Alignment
Pattern Bits
Off
Off
On
Chapter 1: Transceiver Architecture in Arria II Devices
“Byte Serializer” on page 1–14
Word Alignment Pattern
December 2010 Altera Corporation
16'hF628
16'h146F
16'h28F6
Table 1–21
Functional Modes
and
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