EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 534

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

2–44
Arria II Device Handbook Volume 2: Transceivers
1
This configuration uses two FPGA clock resources (global, regional, or both), one for
the tx_clkout[0] signal, and one for the tx_clkout[2] signal.
This example assumes channels 0 and 1, driven by CMU0 PLL in a transceiver block,
are identical. Also, channels 2 and 3, driven by CMU1 PLL in the same transceiver
block, are identical. In this case, the Quartus II software automatically drives the
read port of the receiver phase compensation FIFO in channels 0 and 1 with the
tx_clkout[0] signal. It also drives the read port of the receiver phase
compensation FIFO in channels 2 and 3 with the tx_clkout[2] signal. Use the
tx_clkout[0] signal to latch the receiver data and status signals from channels 0
and 1 in the FPGA fabric. Use the tx_clkout[2] signal to latch the receiver data
and status signals from channels 2 and 3 in the FPGA fabric.
Example 7: Two Groups of Two Identical Channels in a Transceiver Block
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation