EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 92
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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4–20
Figure 4–13. Two-Multiplier Adder Mode Shown for Half-DSP Block
Notes to
(1) In a half-DSP block, you can implement 2 two-multiplier adders.
(2) Block output for accumulator overflow and saturate overflow.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure
Two-Multiplier Adder Sum Mode
4–13:
datab_0[17..0]
dataa_0[17..0]
dataa_1[17..0]
datab_1[17..0]
clock[3..0]
In the two-multiplier adder configuration, the DSP block can implement four 18-bit
two-multiplier adders (2 two-multiplier adders per half-DSP block). You can
configure the adders to take the sum or difference of two multiplier outputs.
Summation or subtraction must be selected at compile time. The two-multiplier adder
function is useful for applications such as FFTs, complex FIR, and IIR filters.
Figure 4–13
The loopback mode is a sub-feature of the two-multiplier adder mode.
shows the DSP block configured in the loopback mode. This mode takes the 36-bit
summation result of the two multipliers and feeds back the most significant 18-bits to
the input. The lower 18-bits are discarded. You have the option to disable or zero-out
the loopback data with the dynamic zero_loopback signal. A logic 1 value on the
zero_loopback signal selects the zeroed data or disables the looped back data, and a
logic 0 selects the looped back data.
ena[3..0]
aclr[3..0]
Half-DSP Block
shows the DSP block configured in the two-multiplier adder mode.
output_saturate
output_round
signa
signb
+
(Note 1)
Chapter 4: DSP Blocks in Arria II Devices
overflow (2)
Arria II Operational Mode Descriptions
December 2010 Altera Corporation
result[ ]
Figure 4–14
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