EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 457

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Table 1–19. Electrical Idle Inference Conditions for Arria II Devices (Part 2 of 2)
December 2010 Altera Corporation
rx_elecidleinfersel[2:0]
3'b110
3'b111
1
The electrical idle inference module cannot detect an electrical idle exit condition
based on the reception of the electrical idle exit ordered set (EIEOS), as specified in the
PCIe Base Specification.
If you select the Enable Electrical Idle Inference Functionality option in the ALTGX
MegaWizard Plug-In Manager and drive rx_elecidleinfersel[2:0] = 3'b0xx, the
electrical idle inference block uses EIOS detection from the fast recovery circuitry to
drive the pipeelecidle signal. Otherwise, the electrical idle inference module is
disabled. In this case, the rx_signaldetect signal from the signal detect circuitry in
the receiver input buffer is inverted and driven as the pipeelecidle signal.
PCIe Cold Reset Requirements
The PCIe Base Specification 2.0 defines the following three types of conventional
resets to the PCIe system components:
■
■
■
Figure 1–69
Figure 1–69. PCIe Cold Reset Requirements
Recovery.Speed when
successful speed
negotiation = 1'b0
Loopback.Active (as slave) Absence of an exit from electrical idle in 128 s window
Cold reset—fundamental reset after power up
Warm reset—fundamental reset without removal and re-application of power
Hot reset—in-band conventional reset initiated by higher layer by setting the hot
reset bit in the TS1 or TS2 training sequences
Power Rail
PERST#
LTSSM State
shows the PCIe cold reset timing requirements.
1
T
PVPERL
Absence of an exit from electrical idle in 2000 UI interval
100 ms
2
T
2-3
T
2-4
3
20 ms
100 ms
Arria II Device Handbook Volume 2: Transceivers
Description
4
Marker 1: Power becomes stable
Marker 2: PERST# gets de-asserted
Marker 3: Maximum time for
the LTSSM to enter the Detect state
Marker 4: Maximum time for
the link to become active
1–71