EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 71

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: Memory Blocks in Arria II Devices
Design Considerations
December 2010 Altera Corporation
Power-Up Conditions and Memory Initialization
Power Management
f
M9K and M144K block outputs power up to zero (cleared), regardless of whether the
output registers are used or bypassed. MLABs power up to zero if the output registers
are used and power up reading the memory contents if the output registers are not
used. You must take this into consideration when designing logic that might evaluate
the initial power-up values of the MLAB memory block. For Arria II devices, the
Quartus II software initializes the RAM cells to zero unless there is a .mif file
specified.
All memory blocks support initialization using a .mif. You can create .mif files in the
Quartus II software and specify their use with the RAM MegaWizard Plug-In
Manager when instantiating a memory in your design. Even if a memory is
pre-initialized (for example, using a .mif), it still powers up with its outputs cleared.
For more information about .mif files, refer to the
Megafunction User Guide
Arria II memory block clock enables allow you to control clocking of each memory
block to reduce AC-power consumption. Use the read-enable signal to ensure that
read operations only occur when you need them to. If your design does not require
read-during-write, you can reduce your power consumption by deasserting the
read-enable signal during write operations or any period when no memory
operations occur.
The Quartus II software automatically places any unused memory block in low power
mode to reduce static power.
and the
Quartus II
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Handbook.
Internal Memory (RAM and ROM)
3–25