EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 588
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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4–14
Figure 4–9. Sample Reset Sequence of Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
Arria II Device Handbook Volume 2: Transceivers
Reset Signals
CDR Control Signals
Output Status Signals
pll_powerdown
rx_analogreset
tx_digitalreset
rx_digitalreset
rx_locktorefclk
rx_pll_locked
rx_locktodata
pll_locked
Receiver and Transmitter Channel—Receiver CDR in Manual Lock Mode
This configuration contains both a transmitter and receiver channel. If you create a
Receiver and Transmitter instance in the ALTGX MegaWizard Plug-In Manager with
the receiver CDR in manual lock mode, use the reset sequence shown in
As shown in
manual lock mode:
1. After power up, assert pll_powerdown for a minimum period of 1 s (the time
2. Keep the tx_digitalreset, rx_analogreset, rx_digitalreset, and
3. After the transmitter PLL locks, as indicated by the pll_locked signal going high
busy
between markers 1 and 2).
rx_locktorefclk signals asserted and the rx_locktodata signal de-asserted
during this time period. After you de-assert the pll_powerdown signal, the
transmitter PLL starts locking to the transmitter input reference clock.
(marker 3), de-assert tx_digitalreset. For receiver operation, wait for the busy
signal to be de-asserted. At this point, rx_analogreset is de-asserted. After
rx_analogreset is de-asserted, the receiver CDR starts locking to the receiver
input reference clock because rx_locktorefclk is asserted.
1
1 μs
Figure
2
4–9, perform the following reset sequence steps for the receiver in
3
Two parallel clock cycles
4
5
6
7
Chapter 4: Reset Control and Power Down in Arria II Devices
15 μs
8
8
4 μs
9
December 2010 Altera Corporation
Transceiver Reset Sequences
Figure
4–9.
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