EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 103
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 4: DSP Blocks in Arria II Devices
Software Support for Arria II Devices
Table 4–9. DSP Block Dynamic Signals for DSP Block in Arria II Devices (Part 2 of 2)
Software Support for Arria II Devices
December 2010 Altera Corporation
shift_right
DSP Block Dynamic Signals per Full-DSP Block
clock0
clock1
clock2
clock3
ena0
ena1
ena2
ena3
aclr0
aclr1
aclr2
aclr3
Total Count per Half- and Full-DSP Blocks
Signal Name
f
f
Altera provides two distinct methods for implementing various modes of the DSP
block in a design: instantiation and inference. Both methods use the following
Quartus II megafunctions:
■
■
■
■
You can instantiate the megafunctions in the Quartus II software to use the DSP block.
Alternatively, with inference, you can create an HDL design and synthesize it with a
third-party synthesis tool (such as LeonardoSpectrum, Synplify, or Quartus II Native
Synthesis) that infers the appropriate megafunction by recognizing multipliers,
multiplier adders, multiplier accumulators, and shift functions. With either method,
the Quartus II software maps the functionality to the DSP blocks during compilation.
For instructions about using the megafunctions and the MegaWizard Plug-In
Manager, refer to the Quartus II Software Help.
For more information, refer to
Handbook.
LPM_MULT
ALTMULT_ADD
ALTMULT_ACCUM
ALTFP_MULT
shift_right = 1, shift right feature is enabled
DSP-block-wide clock signals
Input and Pipeline Register enable signals
DSP block-wide asynchronous clear signals (active low)
Section III: Synthesis
Function
Arria II Device Handbook Volume 1: Device Interfaces and Integration
in volume 1 of the Quartus II
Count
33
1
4
4
4
4–31
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