EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 56

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

3–10
Memory Modes
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Single-Port RAM Mode
1
1
Arria II memory blocks allow you to implement fully synchronous SRAM memory in
multiple modes of operation. M9K and M144K blocks do not support asynchronous
memory (unregistered inputs). MLABs support asynchronous (flow-through) read
operations.
Depending on which memory block you target, you can use the following modes:
■
■
■
■
■
■
To choose the desired read-during-write behavior, set the read-during-write behavior
to either new data, old data, or don't care in the RAM MegaWizard Plug-In Manager
in the Quartus II software. For more information about this behavior, refer to
“Read-During-Write Behavior” on page
When using the memory blocks in ROM, single-port, simple dual-port, or true
dual-port mode, you can corrupt the memory contents if you violate the setup or hold
time on any of the memory block input registers. This applies to both read and write
operations.
All memory blocks support single-port mode. Single-port mode allows you to do
either a one-read or a one-write operation at a time. Simultaneous reads and writes
are not supported in single-port mode.
configuration.
Figure 3–9. Single-Port Memory
Note to
(1) You can implement two single-port memory blocks in a single M9K and M144K blocks. For more information, refer
“Single-Port RAM Mode” on page 3–10
“Simple Dual-Port Mode” on page 3–12
“True Dual-Port Mode” on page 3–15
“Shift-Register Mode” on page 3–17
“ROM Mode” on page 3–18
“FIFO Mode” on page 3–18
to
“Packed Mode Support” on page
Figure
3–9:
data[ ]
address[ ]
wren
byteena[]
addressstall
clockena
rden
aclr
inclock
3–5.
(Note 1)
Figure 3–9
3–21.
shows the single-port RAM
outclock
Chapter 3: Memory Blocks in Arria II Devices
q[]
December 2010 Altera Corporation
Memory Modes