EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 52
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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EP2AGX45DF29I5N
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- EP2AGX45CU17C6N PDF datasheet
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3–6
Figure 3–4. Address Clock Enable During Read Cycle Waveform
Arria II Device Handbook Volume 1: Device Interfaces and Integration
rdaddress
rden
addressstall
latched address
(inside memory)
q (synch)
q (asynch)
inclock
Figure 3–3
addressstall refers to the address clock enable.
Figure 3–3. Address Clock Enable
Figure 3–4
doutn-1
doutn
shows an address clock enable block diagram. The port name
shows the address clock enable waveform during the read cycle.
an
a0
addressstall
address[0]
address[N]
doutn
a0
dout0
clock
a1
dout0
a2
1
0
1
0
a1
dout1
a3
address[N]
address[0]
register
register
dout1
a4
Chapter 3: Memory Blocks in Arria II Devices
a4
dout4
address[N]
a5
address[0]
December 2010 Altera Corporation
dout4
a5
dout5
a6
Memory Features
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