EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 218
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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7–22
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Rules to Combine Groups
f
1
For more information about the ALTMEMPHY megafunction and UniPHY IP core,
refer to the
Use one side of the device with the ×36 mode emulation interface whenever possible,
even though the ×36 group formed by a combination of DQ/DQS groups from the top
and bottom I/O banks, or top/bottom I/O bank and left/right I/O banks is
supported.
In 572-, 780-, 1152-, and some 1517-pin package devices, there is at most one ×16/×18
group per I/O bank. You can combine two ×16/×18 groups from a single side of the
device for a ×36 interface. 358-pin package devices have only one ×16/×18 group in
each bank 4A and 7A. You can only form a ×36 interface with these two banks.
For devices that do not have four ×16/×18 groups in a single side of the device to
form two ×36 groups for read and write data, you can form one ×36 group on one side
of the device and another ×36 group on the other side of the device. Altera
recommends forming two ×36 groups on column I/O banks (top and bottom) only,
although forming a ×36 group from column I/O banks and another ×36 group from
row I/O banks for the read and write data buses is supported. For vertical migration
with the ×36 emulation implementation, you must check if migration is possible by
enabling device migration in the Quartus II project. The Quartus II software also
supports the use of four ×8/×9 DQ groups for write data pins and the migration of
these groups across device density. 358-pin package devices can only form a ×36
group for write data pin with four ×8/×9 groups.
External Memory Interface
Combining ×16/×18 DQ/DQS Groups for ×36 QDR II+/QDR II SRAM Interface
Handbook.
Chapter 7: External Memory Interfaces in Arria II Devices
December 2010 Altera Corporation
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