EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 61
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Manufacturer:
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- EP2AGX45CU17C6N PDF datasheet
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Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Figure 3–15. Mixed-Port Read-During-Write Timing Waveforms
December 2010 Altera Corporation
True Dual-Port Mode
q_a (asynch)
address
byteena
data_a
wrena
rdena
clk_a
Figure 3–15
mode with unregistered outputs.
Arria II M9K and M144K blocks support true dual-port mode. Sometimes called
bidirectional dual-port, this mode allows you to perform any combination of two-port
operations: two reads, two writes, or one read and one write at two different clock
frequencies. True dual-port memory supports input and output clock mode in
addition to the independent clock mode.
Figure 3–16
Figure 3–16. Arria II True Dual-Port Memory
The widest bit configuration of the M9K and M144K blocks in true dual-port mode
are:
■
■
Wider configurations are unavailable because the number of output drivers is
equivalent to the maximum bit width of the respective memory block. Because true
dual-port RAM has outputs on two ports, its maximum width equals half of the total
number of output drivers.
M9K: 512 × 16-bit (or 512 × 18-bit with parity)
M144K: 4K × 32-bit (or 4K × 36-bit with parity)
shows timing waveforms for read and write operations in mixed-port
shows the true dual-port RAM configuration.
A123
01
A0 (old data)
B456
10
data_a[ ]
address_a[ ]
wren_a
byteena_a[]
addressstall_a
enable_a
rden_a
aclr_a
q_a[]
A0
D
clock_a
old
D
old
23
C789
00
Arria II Device Handbook Volume 1: Device Interfaces and Integration
B423
DDDD
A1(old data)
addressstall_b
address_b[]
byteena_b[]
enable_b
data_b[ ]
clock_b
wren_b
rden_b
A1
EEEE
11
aclr_b
q_b[]
DDDD
FFFF
EEEE
3–15
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