EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 59

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode)
Table 3–6. M144K Block Mixed-Width Configurations (Simple Dual-Port Mode)
December 2010 Altera Corporation
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
256 × 32
1K × 9
512 × 18
256 × 36
16K × 8
8K × 16
4K × 32
2K × 64
16K × 9
8K × 18
4K × 36
2K × 72
Read Port
Read Port
Simple dual-port mode supports different read and write data widths (mixed width
support).
dual-port mode. MLABs do not have native support for mixed width operations. The
Quartus II software can implement mixed width memories in MLABs with more than
one MLAB.
Table 3–6
mode.
In simple dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. Read-during-write operations to the same address can either
output a “don’t care” or “old data” value.
MLABs only support a write-enable signal. Read-during-write behavior for the
MLABs can be either a “don’t care” or “old data” value. The available choices depend
on the configuration of the MLAB.
8K × 1
v
v
v
v
v
v
16K × 8
—
—
—
v
v
v
v
—
—
—
—
4K × 2
Table 3–5
lists the mixed-width configurations for M144K blocks in simple dual-port
v
v
v
v
v
v
—
—
—
8K × 16
v
v
v
v
—
—
—
—
2K × 4
lists the mixed width configurations for the M9K blocks in simple
v
v
v
v
v
v
—
—
—
4K × 32
v
v
v
v
—
—
—
—
1K × 8
v
v
v
v
v
v
—
—
—
2K × 64
512 × 16
Arria II Device Handbook Volume 1: Device Interfaces and Integration
v
v
v
v
—
—
—
—
Write Port
v
v
v
v
v
v
—
—
—
Write Port
16K × 9
256 × 32
v
v
v
v
—
—
—
—
v
v
v
v
v
v
—
—
—
8K × 18
1K × 9
v
v
v
v
—
—
—
—
—
—
—
—
—
—
v
v
v
512 × 18
4K × 36
—
—
—
—
—
—
v
v
v
—
—
—
—
v
v
v
v
256 × 36
2K × 72
—
—
—
—
—
—
v
v
v
—
—
—
—
v
v
v
v
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