EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 137
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 5: Clock Networks and PLLs in Arria II Devices
PLLs in Arria II Devices
December 2010 Altera Corporation
Post-Scale Counter Cascading
1
The VCO frequency reported by the Quartus II software is the value after the
post-scale counter divider (K).
Each PLL has one pre-scale counter (N) and one multiply counter (M) with a range of
1 to 512 for both M and N. The n counter does not use duty-cycle control because the
only purpose of this counter is to calculate frequency division. There are seven generic
post-scale counters in each PLL that can feed GCLKs, RCLKs, or external clock
outputs. These post-scale counters range from 1 to 512 with a 50% duty cycle setting.
The high- and low-count values for each counter ranges from 1 to 256. The sum of the
high- and low-count values chosen for a design selects the divide value for a given
counter.
The Quartus II software automatically chooses the appropriate scaling factors
according to the input frequency, multiplication, and division values entered into the
ALTPLL megafunction.
Arria II PLLs support post-scale counter cascading to create counters larger than 512.
This is automatically implemented in the Quartus II software by feeding the output of
one C counter into the input of the next C counter, as shown in
Figure 5–28. Counter Cascading for Arria II Devices
Note to
(1) n = 6 for Arria II GX devices. n = 6 or 9 for Arria II GZ devices.
When cascading post-scale counters to implement a larger division of the
high-frequency VCO clock, the cascaded counters behave as one counter with the
product of the individual counter settings. For example, if C0 = 40 and C1 = 20, the
cascaded value is C0 × C1 = 800.
Post-scale counter cascading is set in the configuration file. You cannot accomplish
post-scale counter cascading with PLL reconfiguration.
Figure
5–28:
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
Arria II Device Handbook Volume 1: Device Interfaces and Integration
C0
C1
C2
C3
C4
Cn
(1)
from preceding
post-scale counter
Figure
5–28.
5–33
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