EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 274
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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EP2AGX45DF29I5N
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ALTERA
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EP2AGX45DF29I5N
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8–34
Arria II Device Handbook Volume 1: Device Interfaces and Integration
A corner PLL and a center PLL can drive duplex channels in the same I/O bank, if the
channels driven by each PLL are not interleaved. No separation is necessary between
the group of channels driven by the corner and center left and right PLLs. Refer to
Figure 8–27
Figure 8–28. Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels
Driven by the Corner and Center PLLs
and
Figure
8–28.
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
DPA-disabled
Reference CLK
Reference CLK
DPA-disabled
DPA-disabled
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Diff I/O
Center
Center
PLL
PLL
Differential Pin Placement Guidelines
December 2010 Altera Corporation
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