EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 482
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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1–96
Table 1–24. ALTGX Megafunction Word Aligner Ports for Arria II Devices (Part 2 of 2)
Table 1–25. ALTGX Megafunction Deskew FIFO Port for Arria II Devices
Table 1–26. ALTGX Megafunction Rate Match (Clock Rate Compensation) FIFO Ports for Arria II Devices (Part 1 of 2)
Arria II Device Handbook Volume 2: Transceivers
rx_rlv
rx_syncstatus
rx_channelaligned
rx_rmfifodatadeleted
rx_rmfifodatainserted
Port Name
Port Name
Port Name
Table 1–25
megafunction.
Table 1–26
descriptions for the ALTGX megafunction.
Input/Output
Input/Output
Input/Output
Output
Output
Output
Output
Output
lists the deskew FIFO port name and description for the ALTGX
lists the rate match (clock rate compensation) FIFO port names and
Asynchronous run-length violation indicator. A high pulse is driven when the
number of consecutive 1s or 0s in the received data stream exceeds the
programmed run length violation threshold.
This signal is driven for a minimum of two recovered clock cycles in
configurations without byte serializer and a minimum of three recovered clock
cycles in configurations with byte serializer.
Word alignment synchronization status indicator. For word aligner in automatic
synchronization state machine mode, this signal is driven high if the conditions
required to remain in synchronization are met.
For word aligner in manual alignment mode, this signal is driven high for one
parallel clock cycle synchronous to the MSByte of the word alignment pattern.
This signal is not available for word aligner in bit-slip mode.
The width of this signal depends on the channel width shown below:
Channel Width
Indicates whether all the channels are aligned. This signal is only available in
XAUI mode. A high level indicates that the XAUI deskew state machine is either
in a ALIGN_ACQUIRED_1, ALIGN_ACQUIRED_2, ALIGN_ACQUIRED_3, or
ALIGN_ACQUIRED_4 state, as specified in the PCS deskew state diagram in
IEEE P802.3ae specification.
A low level indicates that the XAUI deskew state machine is either in a
LOSS_OF_ALIGNMENT, ALIGN_DETECT_1, ALIGN_DETECT_2, or
ALIGN_DETECT_3 state, as specified in the PCS deskew state diagram in IEEE
P802.3ae specification.
Rate match FIFO deletion status indicator. A high level indicates that the rate
match pattern byte was deleted to compensate for the PPM difference in
reference clock frequencies between the upstream transmitter and the local
receiver.
Rate match FIFO insertion status indicator. A high level indicates that the rate
match pattern byte was inserted to compensate for the PPM difference in
reference clock frequencies between the upstream transmitter and the local
receiver.
16/20
8/10
rx_syncstatus width
1
2
Chapter 1: Transceiver Architecture in Arria II Devices
Description
Description
Description
December 2010 Altera Corporation
Transceiver Port List
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