EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 115
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Table 5–6. PLLs and PLL Clock Pin Drivers for Arria II GX Devices
Table 5–7. PLLs and PLL Clock Pin Drivers for Arria II GZ Devices
December 2010 Altera Corporation
CLK[4..7]
CLK[8..11]
CLK[12..15]
Note to
(1) PLL_5 and PLL_6 are connected directly to CLK[8..11]. PLL_1, PLL_2, PLL_3 and PLL_4 are driven by the clock input pins through a 4:1
CLK[0..3]
CLK[4..7]
CLK[8..11]
CLK[12..15]
Notes to
(1) For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the CLK<#>n pin, a GCLK is used.
(2) For the availability of the clock input pins in each device density, refer to the “Arria II Device Pin-Out Files” section of the
Dedicated Clock Input Pin CLK
multiplexer.
Devices.
Dedicated Clock Input Pin CLK (p/n Pins)
Table
Table
Clock Input Connections to PLLs
Clock Output Connections
5–6:
5–7:
(p/n Pins)
Table 5–6
PLLs in Arria II GX devices can drive up to 24 RCLK networks and eight GCLK
networks, while PLLs in Arria II GZ devices can drive up to 20 RCLK networks and
four GCLK networks. The Quartus
outputs to RCLK or GCLK networks.
and
Table 5–7
—
—
—
L2
v
list dedicated clock input pin connectivity to Arria II PLLs.
—
—
—
L3
v
—
—
v
1
®
B1
v
—
—
—
Arria II Device Handbook Volume 1: Device Interfaces and Integration
II software automatically assigns PLL clock
(Note
(Note 1)
—
2
v
v
1),
B2
—
—
—
v
PLL Number
(2)
PLL Number
—
3
v
v
R2
—
—
—
v
—
—
v
4
R3
—
—
—
v
Pin-Out Files for Altera
—
—
v
5
v
T1
—
—
—
—
—
v
6
T2
—
—
—
v
5–11
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