EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 33
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Adaptive Logic Modules
Adaptive Logic Modules
Figure 2–5. High-Level Block Diagram of the Arria II ALM
December 2010 Altera Corporation
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
The ALM is the basic building block of logic in the Arria II device architecture. Each
ALM contains a variety of LUT-based resources that can be divided between two
combinational adaptive LUTs (ALUTs) and two registers. With up to eight inputs for
the two combinational ALUTs, one ALM can implement various combinations of two
functions. This adaptability allows an ALM to be completely backward-compatible
with 4-input LUT architectures. One ALM can also implement any function with up
to 6-input and certain 7-input functions. In addition to the ALUT-based resources,
each ALM contains two programmable registers, two dedicated full adders, a carry
chain, a shared arithmetic chain, and a register chain. Through these dedicated
resources, an ALM can efficiently implement various arithmetic functions and shift
registers. Each ALM drives all types of interconnects: local, row, column, carry chain,
shared arithmetic chain, register chain, and direct link.
block diagram of the Arria II ALM.
Combinational/Memory ALUT1
Combinational/Memory ALUT0
shared_arith_out
shared_arith_in
6-Input LUT
6-Input LUT
carry_in
carry_out
adder0
adder1
Arria II Device Handbook Volume 1: Device Interfaces and Integration
reg_chain_in
reg_chain_out
labclk
D
D
reg0
reg1
Figure 2–5
Q
Q
To general or
To general or
To general or
To general or
local routing
local routing
local routing
local routing
shows a high-level
2–5
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