EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 494
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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2–4
Arria II Device Handbook Volume 2: Transceivers
Table 2–1
on the refclk pins.
Table 2–1. Electrical Specifications for the Input Reference Clock for Arria II Devices
Figure 2–3
configured as HCSL.
Figure 2–3. Termination Scheme for a Reference Clock Signal When Configured as HCSL
Notes to
(1) No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe
(2) Select resistor values as recommended by the PCIe clock source vendor.
■
■
■
■
■
■
Notes to
(1) In PCI Express
(2) For an example termination scheme, refer to
(Note 1)
PCI Express (PIPE)
GIGE
XAUI
Serial RapidIO
SONET/SDH
SDI
Basic
specification.
if compliance to the PCIe protocol is required. The Quartus
external termination for the refclk pins signal if configured as HCSL.
Protocol
Figure
(1),
Table
lists the electrical specifications for the input reference clock signal driven
shows an example termination scheme for a reference clock signal when
(2)
2–1:
2–3:
REFCLK
(HCSL)
Source
PCIe
®
®
(PIPE) (PCIe) mode, you have the option of selecting the HCSL standard for the reference clock
■
■
■
■
■
■
■
■
■
■
1.2-V PCML
1.5-V PCML
2.5-V PCML
Differential LVPECL
LVDS
1.2-V PCML
1.5-V PCML
2.5-V PCML
DIfferential LVPECL
LVDS
I/O Standard
HCSL
Rp
Rs
Rs
=
(2)
(2)
50 Ω
Figure
2–3.
®
CMU PLL and Receiver CDR Input Reference Clocking
Chapter 2: Transceiver Clocking in Arria II Devices
II software automatically selects DC coupling with
Rp
Coupling
=
DC
AC
AC
50 Ω
December 2010 Altera Corporation
REFCLK
REFCLK
Arria II
Termination
+
-
Off-chip
On-chip
On-chip
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