EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 107

• Manufacturer Part Number: EP2AGX45DF29I5
• Description: IC ARRIA II GX FPGA 45K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX45DF29I5

• Number Of Logic Elements/cells: 42959
• Number Of Labs/clbs: 1805
• Total Ram Bits: 3435
• Number Of I /o: 364
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Figure 5–1. GCLK Networks in Arria II GX Devices
Notes to
(1) PLL_5 and PLL_6 are only available in EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.
(2) Because there are no dedicated clock pins on the left side of an Arria II GX device, GCLK[0..3] are not driven by any clock pins.
December 2010 Altera Corporation
Figure
Top Left PLL
Bottom Left PLL
Global Clock Networks
5–1:
Arria II devices provide up to 16 GCLKs that can drive throughout the device, serving
as low-skew clock sources for functional blocks such as adaptive logic modules
(ALMs), digital signal processing (DSP) blocks, embedded memory blocks, and PLLs.
Arria II I/O elements (IOEs) and internal logic can drive GCLKs to create internally
generated GCLKs and other high fan-out control signals; for example, synchronous or
asynchronous clears and clock enables.
PLLs that can drive GCLK networks in Arria II devices.
PLL_1
PLL_4
GCLK[0..3] ( 2 )
GCLK[12..15]
GCLK[4..7]
CLK[4..7]
CLK[12..15]
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Figure 5–1
GCLK[8..11]
and
Figure 5–2
PLL_2
PLL_5
PLL_6
PLL_3
Bottom Right PLL
(1)
(1)
show CLK pins and
Top Right PLL
Center PLLs
CLK[8..11]
5–3