EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 46
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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2–18
Document Revision History
Table 2–1. Document Revision History
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
June 2009
February 2009
Date
f
Version
■
For more information about implementing static and dynamic power consumption
within the LAB, refer to the
Handbook.
Table 2–1
2.0
1.1
1.0
Clocks represent a significant portion of dynamic power consumption due to their
high switching activity and long paths. The LAB clock that distributes a clock
signal to registers within an LAB is a significant contributor to overall clock power
consumption. Each LAB’s clock and clock enable signal are linked. For example, a
combinational ALUT or register in a particular LAB using the labclk1 signal also
uses the labclkena1 signal. To disable an LAB-wide clock power consumption
without disabling the entire clock tree, use the LAB-wide clock enable to gate the
LAB-wide clock. The Quartus II software automatically promotes register-level
clock enable signals to the LAB-level. All registers within the LAB that share a
common clock and clock enable are controlled by a shared, gated clock. To take
advantage of these clock enables, use a clock-enable construct in your HDL code
for the registered logic.
Updated for the Quartus II software version 10.1 release:
■
■
■
■
Updated Figure 2–6.
Initial Release.
Added Arria II GZ device information.
Updated
Logic
Added
Added
lists the revision history for this document.
Modules”,
Figure 2–7
“LAB Power Management Techniques”
“Logic Array
“ALM Operating
and
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II Devices
Power Optimization
Blocks”,
Figure
2–8.
“LAB
Modes”,
Interconnects”,
Changes
“Normal Mode”
chapter in volume 2 of the Quartus II
section.
“LAB Control
sections.
December 2010 Altera Corporation
Signals”,
Document Revision History
“Adaptive
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