EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 449
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Table 1–15. Supported Features in PCIe Mode for Arria II Devices (Part 1 of 2)
December 2010 Altera Corporation
×1, ×4, ×8 link configurations
PCIe-compliant synchronization state machine
±300 PPM (total 600 PPM) clock rate compensation
8-bit FPGA fabric-transceiver interface
16-bit FPGA fabric-transceiver interface
Transmitter buffer electrical idle
Receiver detection
8B/10B encoder disparity control when transmitting compliance pattern
Power state management
Receiver status encoding
f
f
For descriptions of PCIe hard IP architecture and PCIe mode configurations allowed
when using the PCIe hard IP block, refer to the
For more information about transceiver datapath clocking in different PCIe
configurations, refer to the
The transmitter datapath in PCIe mode consists of the:
■
■
■
■
■
■
The receiver datapath in PCIe mode consists of the:
■
■
■
■
■
■
■
■
Table 1–15
Gen2 (5.0 Gbps) data rate configurations.
PIPE interface
TX phase compensation FIFO
Optional byte serializer (enabled for 16-bit and disabled for 8-bit FPGA
fabric-transceiver interface)
8B/10B encoder
10:1 serializer
Transmitter buffer with receiver detect circuitry
Receiver input buffer with signal detect circuitry
1:10 deserializer
Word aligner that implements PCIe-compliant synchronization state machine
Optional rate match FIFO (clock rate compensation) that can tolerate up to
600 PPM frequency difference
8B/10B decoder
Optional byte deserializer (enabled for 16-bit and disabled for 8-bit FPGA
fabric-transceiver interface)
RX phase compensation FIFO
PIPE interface
Feature
lists features supported in PCIe functional mode for Gen1 (2.5 Gbps) and
Transceiver Clocking in Arria II Devices
PCI Express Compiler User
2.5 Gbps (Gen1)
Arria II Device Handbook Volume 2: Transceivers
v
v
v
v
v
v
v
v
v
v
chapter.
5.0 Gbps (Gen2)
Only ×1 and ×4 are
supported
Guide.
v
v
v
v
v
v
v
v
—
(1)
1–63
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