EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 242
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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8–2
LVDS Channels
Arria II Device Handbook Volume 1: Device Interfaces and Integration
f
f
1
For specifications and features of the differential I/O standards supported in Arria II
devices, refer to the
chapters.
In Arria II GX devices, there are true LVDS input buffers and LVDS I/O buffers at the
top, bottom, and right side of the device. The LVDS input buffers have 100-Ω on-chip
differential termination (R
either LVDS input (without R
configure the LVDS pins on the top, bottom, and right sides of the device, as emulated
LVDS output buffers, which use two single-ended output buffers with an external
resistor network to support LVDS, mini-LVDS, and RSDS standards.
The Arria II GZ devices support LVDS on both row and column I/O banks. Row I/Os
support true LVDS input with 100-Ω R
I/Os supports true LVDS input buffers without R
row and column LVDS pins as emulated LVDS output buffers that use two single-
ended output buffers with an external resistor network to support LVDS, mini-LVDS,
and RSDS standards. Arria II GZ devices offer single-ended I/O refclk support for
the LVDS.
Dedicated SERDES and DPA circuitries are implemented on the right I/O banks of
Arria II GX devices and row I/O banks of Arria II GZ devices to further enhance the
LVDS interface preformance in the device. For column I/O banks in Arria II devices,
SERDES is implementated in the core logic because there is no dedicated SERDES
circuitry.
When you configure the I/O buffers as LVDS input with R
set both the V
For more information about I/O banks, refer to the
chapter.
CCIO
and V
I/O Features in Arria II Devices
CCPD
D
OCT) support. You can configure the LVDS I/O buffers as
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
D
to 2.5 V.
OCT) or true LVDS output buffers. You can also
D
OCT, and true LVDS output buffers. Column
D
and
OCT. You can also configure the
I/O Features in Arria II Devices
Arria II Devices Data Sheet
D
December 2010 Altera Corporation
OCT enabled, you must
LVDS Channels
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