EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 90
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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4–18
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Double Multiplier
You can configure the Arria II DSP block to support an unsigned 54 × 54-bit multiplier
that is required to compute the mantissa portion of an IEEE double precision floating
point multiplication. You can build a 54 × 54-bit multiplier with basic 18 × 18
multipliers, shifters, and adders. To efficiently use built-in shifters and adders in the
Arria II DSP block, a special double mode (partial 54 × 54 multiplier) is available that
is a slight modification to the basic 36 × 36 multiplier mode, as shown in
and
Figure 4–11. Double Mode Shown for a Half DSP Block
dataa_0[35..18]
datab_0[35..18]
datab_0[35..18]
dataa_0[35..18]
datab_0[17..0]
dataa_0[17..0]
dataa_0[17..0]
datab_0[17..0]
Figure
clock[3..0]
ena[3..0]
aclr[3..0]
4–12.
Half-DSP Block
signa
signb
+
+
+
Chapter 4: DSP Blocks in Arria II Devices
Arria II Operational Mode Descriptions
December 2010 Altera Corporation
72
Figure 4–11
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