EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 58
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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3–12
Figure 3–11. Timing Waveform for Read-Write Operations for MLABs (Single-Port Mode
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Simple Dual-Port Mode
q_a (asynch)
address_a
Figure 3–11
mode with unregistered outputs for the MLAB. The rising clock edges trigger the read
operation whereas the falling clock edges triggers the write operation.
data_a
All memory blocks support simple dual-port mode. Simple dual-port mode allows
you to perform one-read and one-write operation to different locations at the same
time. The write operation occurs on port A; the read operation occurs on port B.
Figure 3–12
input and output clock mode in addition to the read and write clock mode.
Figure 3–12. Arria II Simple Dual-Port Memory
Note to
(1) Only available for Arria II GZ devices.
wrena
rdena
clk_a
Figure
3–12:
shows the timing waveforms for read and write operations in single-port
shows a simple dual-port configuration. Simple dual-port RAM supports
(old data)
A
a0
A
a0
B
data[ ]
wraddress[ ]
wren
byteena[]
wr_addressstall
wrclock
wrclocken
aclr
C
B
C
(old data)
D
a1
rd_addressstall
ecc_status (1)
rdaddress[ ]
rdclocken
a1
E
rdclock
D
Chapter 3: Memory Blocks in Arria II Devices
rden
q[ ]
)
December 2010 Altera Corporation
F
E
Memory Modes
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