EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 491
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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AIIGX52002-3.0
CMU PLL and Receiver CDR Input Reference Clocking
Arria II Device Handbook Volume 2: Transceivers
December 2010
December 2010
AIIGX52002-3.0
This chapter describes the Arria
including the input reference clocking, transceiver channel datapath clocking, FPGA
fabric-transceiver interface clocking, and FPGA fabric phase-locked loop
(PLL)-transceiver PLL cascading.
This chapter includes the following sections:
■
■
■
■
■
Each transceiver block in the Arria II GX and GZ device contains the following:
■
■
The CMU PLLs and receiver CDRs require an input reference clock to operate. The
CMU PLL synthesizes the input reference clock to generate the high-speed serial clock
used in the transmitter physical media attachment (PMA). The receiver CDR uses the
input reference clock as a training clock when it is in lock-to-reference (LTR) mode.
The CMU PLLs and receiver CDRs in each transceiver block can derive input
reference from one of the following sources:
■
■
■
■
“CMU PLL and Receiver CDR Input Reference Clocking”
“Transceiver Channel Datapath Clocking” on page 2–6
“FPGA Fabric-Transceiver Interface Clocking” on page 2–28
“FPGA Fabric PLL-Transceiver PLL Cascading” on page 2–56
“Using the CMU PLL for Clocking User Logic in the FPGA Fabric” on page 2–66
Two clock multiplier unit (CMU) PLLs (CMU0 PLL and CMU1 PLL)
Four clock data recovery (CDR) units, one in each receiver channel
refclk0 and refclk1 pins of the same transceiver block
refclk0 and refclk1 pins of other transceiver blocks on the same side of the
device using the inter-transceiver block (ITB) clock network
Dedicated CLK input pins on the FPGA global clock network
Clock output pins from the left-side PLLs (PLL_1 and PLL_4) in the FPGA fabric
2. Transceiver Clocking in Arria II
®
II GX and GZ transceiver clocking architecture,
Devices
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