EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 24
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EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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1–10
Arria II Device Handbook Volume 1: Device Interfaces and Integration
DSP Resources
I/O Features
Table 1–6
Table 1–6. Memory Modes for Arria II Devices
■
■
■
■
■
■
Table 1–7. I/O Standards Support for Arria II Devices
■
■
Single Port
Simple Dual Port
True Dual Port
Single-Ended I/O
Differential I/O
Note to
(1) BLVDS is only available for Arria II GX devices.
Fulfills the DSP requirements of 3G and Long Term Evolution (LTE) wireless
infrastructure applications, video processing applications, and voice processing
applications
DSP block input registers efficiently implement shift registers for finite impulse
response (FIR) filter applications
The Quartus II software includes megafunctions you can use to control the mode
of operation of the DSP blocks based on user-parameter settings
You can directly infer multipliers from the VHDL or Verilog HDL source code
Contains up to 20 modular I/O banks
All I/O banks support a wide range of single-ended and differential I/O
standards listed in
Supports programmable bus hold, programmable weak pull-up resistors, and
programmable slew rate control
For Arria II devices, calibrates OCT or driver impedance matching for
single-ended I/O standards with one OCT calibration block on the I/O banks
listed in
Port Mode
Table
Type
lists the Arria II device memory modes.
1–7:
Table
1–8.
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, ×36, ×64, and ×72
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, ×36, ×64, and ×72
×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
LVTTL, LVCMOS, SSTL, HSTL, PCIe, and PCI-X
SSTL, HSTL, LVPECL, LVDS, mini-LVDS, Bus LVDS (BLVDS) (1), and
RSDS
Table
1–7.
Port Width Configuration
I/O Standard
Chapter 1: Overview for the Arria II Device Family
December 2010 Altera Corporation
Arria II Device Architecture
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