EP2AGX45DF29I5 Altera, EP2AGX45DF29I5 Datasheet - Page 181
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX45DF29I5
Manufacturer Part Number
EP2AGX45DF29I5
Description
IC ARRIA II GX FPGA 45K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
Specifications of EP2AGX45DF29I5
Number Of Logic Elements/cells
42959
Number Of Labs/clbs
1805
Total Ram Bits
3435
Number Of I /o
364
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Manufacturer:
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Chapter 6: I/O Features in Arria II Devices
OCT Support
December 2010 Altera Corporation
f
R
All I/O banks in Arria II GX devices support input R
value of 100 Ω , as shown in
support R
V.
Arria II GZ column I/O banks and dedicated clock input pairs on the row I/O banks
do not support R
when both the V
Figure 6–7. Differential Input On-Chip Termination for Arria II Devices
For more information about R
with DPA in Arria II Devices
R
Arria II GZ devices support R
calibration is only supported for input configuration of input and bidirectional pins.
Output pin configurations do not support R
R
I/O standard of the pin where the R
Figure 6–8. R
D
T
T
OCT with calibration. When you use R
OCT with Calibration for Arria II GZ Devices
OCT for Arria II LVDS Input I/O Standard
D
OCT. You can enable R
T
Transmitter
OCT with Calibration for Arria II GZ Devices
CCIO
D
Transmitter
OCT. You can enable the Arria II GZ R
and V
CCPD
Figure
chapter.
T
D
OCT with calibration in all banks. R
OCT, refer to the
is set to 2.5 V.
6–7. However, not all input differential pins
D
T
Arria II Device Handbook Volume 1: Device Interfaces and Integration
OCT when both the V
Z
OCT is enabled.
Z
Z
O
O
O
= 50
= 50 Ω
= 50 Ω
T
OCT, the V
T
OCT with calibration.
V
REF
High-Speed Differential I/O Interfaces
D
CCIO
V
OCT with a nominal resistance
CCIO
GND
D
100
Arria II GZ OCT
100
of the bank must match the
CCIO
100 Ω
OCT in row I/O banks
Receiver
and V
Receiver
T
Figure 6–8
OCT with
CCPD
is set to 2.5
shows
6–23
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