MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 114
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Memory Map
2-10
0x0_301C–
0x0_300C
0x0_30FF
0x0_310C
0x0_3000
0x0_3004
0x0_3008
0x0_3010
0x0_3014
0x0_3100
0x0_3104
0x0_3108
0x140–
0x150–
0xBFC
0x10C
0x11C
0xBF4
0xBF8
0x084
0x100
0x104
0x108
0x110
0x114
0x118
0x120
0x124
0x128
0x130
0x144
0x148
Offset
CS1_CONFIG—Chip select 1 configuration
TIMING_CFG_3—DDR SDRAM timing configuration 3
TIMING_CFG_0—DDR SDRAM timing configuration 0
TIMING_CFG_1—DDR SDRAM timing configuration 1
TIMING_CFG_2—DDR SDRAM timing configuration 2
DDR_SDRAM_CFG—DDR SDRAM control configuration
DDR_SDRAM_CFG_2—DDR SDRAM control
configuration 2
DDR_SDRAM_MODE—DDR SDRAM mode configuration
DDR_SDRAM_MODE_2—DDR SDRAM mode
configuration 2
DDR_SDRAM_MD_CNTL—DDR SDRAM mode control
DDR_SDRAM_INTERVAL—DDR SDRAM interval
configuration
DDR_DATA_INIT—DDR SDRAM data initialization
DDR_SDRAM_CLK_CNTL—DDR SDRAM clock control
Reserved
DDR_INIT_ADDR—DDR training initialization address
Reserved
DDR_IP_REV1—DDR IP block revision 1
DDR_IP_REV2—DDR IP block revision 2
I2C1ADR—I
I2C1FDR—I
I2C1CR—I
I2C1SR—I
I2C1DR—I
I2C1DFSRR—I
Reserved, should be cleared
I2C2ADR—I
I2C2FDR—I
I2C2CR—I
I2C2SR—I
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
2
2
2
2
2
C1 status register
C2 status register
C1 control register
C1 data register
C2 control register
2
2
2
2
C1 frequency divider register
C2 frequency divider register
C1 address register
C2 address register
2
C1 digital filter sampling rate register
Register
Table 2-2. Memory Map (continued)
I
I
2
2
C1 Controller
C2 Controller
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
R
R
0x nnnn _ nnnn
0x00 nn _00 nn
0x0000_0000
0x0000_0000
0x0011_0105
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0200_0000
0x0000_0000
Reset
0x00
0x00
0x00
0x81
0x00
0x10
0x00
0x00
0x00
0x81
—
—
—
12
12
Freescale Semiconductor
Section/Page
9.4.1.10/9-23
9.4.1.11/9-24
9.4.1.12/9-26
9.4.1.13/9-27
9.4.1.14/9-27
9.4.1.15/9-28
9.4.1.16/9-28
9.4.1.17/9-29
17.3.1.1/17-5
17.3.1.2/17-6
17.3.1.3/17-7
17.3.1.4/17-8
17.3.1.5/17-9
17.3.1.6/17-9
17.3.1.1/17-5
17.3.1.2/17-6
17.3.1.3/17-7
17.3.1.4/17-8
9.4.1.2/9-10
9.4.1.3/9-11
9.4.1.4/9-12
9.4.1.5/9-14
9.4.1.6/9-16
9.4.1.7/9-18
9.4.1.8/9-21
9.4.1.9/9-22
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