MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 534
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Enhanced Local Bus Controller
Figure 10-67
10.4.4.4.9
When the LAST bit is read in a RAM word, the current UPM pattern is terminated at the end of the current
cycle. On the next cycle (following LAST) all the UPM signals are negated unconditionally (driven to
logic 1), unless there is a back-to-back UPM request pending. In this case, the signal values for the cycle
following the one in which the LAST bit was set are taken from the first RAM word of the pending UPM
routine.
In case of UPM writes, program UTA and LAST in same RAM word. In case of UPM reads, program UTA
and LAST in consecutive or same RAM words.
10.4.4.4.10 Wait Mechanism (WAEN)
The WAEN bit in the RAM array word can be used to enable the UPM wait mechanism in selected UPM
RAM words. If the UPM reads a RAM word with WAEN set, the external LUPWAIT signal is sampled
and synchronized by the memory controller as if it were an asynchronous signal. The WAEN bit is ignored
if LAST = 1 in the same RAM word.
Synchronization of LUPWAIT starts at the rising edge of the bus clock and takes at least 1 bus cycle to
complete. If LUPWAIT is asserted and WAEN = 1 in the current UPM word, the UPM is frozen until
LUPWAIT is negated. The value of external signals driven by the UPM remains as indicated in the
previous RAM word. When LUPWAIT is negated, the UPM continues normal functions. Note that during
WAIT cycles, the UPM does not handle data.
10-86
•
•
To internal
data bus
If M
latched on the falling edge of the bus clock instead of the rising edge. The eLBC samples the data
on the next falling edge of the bus clock, which is during the middle of the current bus cycle. This
feature should be used only in systems without external synchronous bus devices that require
mid-cycle sampling.
If M
the RAM word, data is latched on the rising edge of the bus clock, which occurs at the end of the
current bus clock cycle (normal operation).
x
x
MR[GPL4] = 1 (G4T4/DLT3 functions as DLT3) and DLT3 = 1 in the RAM word, data is
MR[GPL4] = 0 (G4T4/DLT3 functions as G4T4), or if M
shows how data sampling is controlled by the UPM.
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
LGPL[0:5] Signal Negation (LAST)
UPM read AND GPL4nDIS = 1 AND DLT3 = 1
Figure 10-67. UPM Read Access Data Sampling
M
U
O
R
L
T
P
L
E
X
I
1
0
LCLK
x
MR[GPL4] = 1 but DLT3 = 0 in
Freescale Semiconductor
LAD[0:15]
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