MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 41
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Figure
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Freescale Semiconductor
Power Management Controller Event Register .................................................................... 5-67
Power Management Controller Mask Register ..................................................................... 5-69
Power Management Controller Configuration Register 1 .................................................... 5-70
Power Management Controller Configuration Register 2 .................................................... 5-71
Power Segmentation in Deep Sleep Mode............................................................................ 5-74
Power State Transitions Supported ....................................................................................... 5-83
Example VDD Control of Device as Agent Using the Optional PMC_PWR_OK Signal ... 5-89
Example VDD Control of Device as Host ............................................................................ 5-89
Arbiter Configuration Register (ACR) ................................................................................... 6-2
Arbiter Timers Register (ATR) ............................................................................................... 6-4
Arbiter Event Register (AER)................................................................................................. 6-5
Arbiter Interrupt Definition Register (AIDR) ......................................................................... 6-6
Arbiter Mask Register (AMR) ................................................................................................ 6-7
Arbiter Event Attributes Register (AEATR) ........................................................................... 6-8
Arbiter Event Address Register (AEADR) ............................................................................. 6-9
Arbiter Event Response Register (AERR)............................................................................ 6-10
Address Bus Arbitration........................................................................................................ 6-11
An Example of Priority-Based Arbitration Algorithm ......................................................... 6-12
e300c3 Core Block Diagram................................................................................................... 7-2
e300 Programming Model—Registers.................................................................................. 7-15
e300c3 Data Cache Organization.......................................................................................... 7-29
Core Interface........................................................................................................................ 7-37
Interrupt Sources Block Diagram ........................................................................................... 8-3
System Global Interrupt Configuration Register (SICFR) ..................................................... 8-7
System Global Interrupt Vector Register (SIVCR)................................................................. 8-9
System Internal Interrupt Pending Register (SIPNR_H) ...................................................... 8-11
System Internal Interrupt Pending Register (SIPNR_L)....................................................... 8-12
System Internal Interrupt Group A Priority Register (SIPRR_A) ........................................ 8-14
System Internal Interrupt Group D Priority Register (SIPRR_D) ........................................ 8-14
System Internal Interrupt Mask Register (SIMSR_H).......................................................... 8-15
System Internal Interrupt Mask Register (SIMSR_L) .......................................................... 8-16
System Internal Interrupt Control Register (SICNR) ........................................................... 8-17
System External Interrupt Pending Register (SEPNR)......................................................... 8-18
System Mixed Interrupt Group A Priority Register (SMPRR_A) ........................................ 8-18
System Mixed Interrupt Group B Priority Register (SMPRR_B) ........................................ 8-19
System External Interrupt Mask Register (SEMSR) ............................................................ 8-20
System External Interrupt Control Register (SECNR) ......................................................... 8-21
System Error Status Register (SERSR)................................................................................. 8-22
System Error Mask Register (SERMR) ................................................................................ 8-24
System Error Control Register (SERCR).............................................................................. 8-24
System Internal Interrupt Force Register (SIFCR_H) .......................................................... 8-25
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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