MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 574

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DMA/Messaging Unit
12.3.8.6
DMABCRn contains the number of bytes per transfer (maximum transfer size is 64 Mbytes).
shows the DMABCRn.
Table 12-15
12.3.8.7
DMANDARn contains the address for the next segment descriptor in the chain. In chaining mode, this
register is loaded from the ‘next descriptor’ field of the descriptor to which the current descriptor address
register is pointing.
Table 12-16
12-14
Offset 0x124, 0x1A4, 0x224, 0x2A4
Reset
Offset 0x120, 0x1A0, 0x220, 0x2A0
Reset
31–26
25–0
31–5
Bits
Bits
4
3
W
R
W
R
31
31
NEOSIE Next end-of-segment interrupt enable.
Name
NSNEN Next snoop enable.
Name
BC
NDA
—
describes the DMABCRn register.
describes the DMANDARn register.
DMA Byte Count Register (DMABCR n )
DMA Next Descriptor Address Register (DMANDAR n )
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
—
Reserved
Byte count. This field contains the number of bytes to transfer. The value in this register is decremented after
each DMA read operation. Maximum transfer size is 64 Mbytes.
Next descriptor address. This field contains the next descriptor address of the next segment descriptor in
memory. It must be aligned on an 8-word boundary.
0 Snooping is disabled on DMA transactions.
1 Snooping is enabled on DMA transactions.
0 No end-of-segment interrupt is generated.
1 An interrupt is generated when the DMA transfer for the next descriptor is finished.
Figure 12-16. DMA Next Descriptor Address Register (DMANDAR n )
Figure 12-16
26 25
Figure 12-15. DMA Byte Count Register (DMABCR n )
Table 12-16. DMANDAR n Field Descriptions
Table 12-15. DMABCR n Field Descriptions
shows the DMANDARn.
NDA
All zeros
All zeros
Description
Descriptions
BC
5
NSNEN NESIE
4
Access: User Read/Write
Access: User Read/Write
Freescale Semiconductor
3
Figure 12-15
2
—
1
EOTD
0
0