MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 396

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

DDR Memory Controller
Figure 9-1
Section 9.5, “Functional Description,”
9.2
The DDR memory controller includes these distinctive features:
9-2
•
•
•
•
•
•
•
Request from
Address from
Support for DDR2 and DDR SDRAM
32-bit SDRAM, 16-bit SDRAM for DDR and DDR2
Programmable settings for meeting all SDRAM timing parameters
The following SDRAM configurations are supported:
— As many as two physical banks (chip selects), each bank independently addressable
— 64-Mbit to 4-Gbit devices depending on internal device configuration with x8/x16/x32 data
— Unbuffered and registered DRAM modules
Open page management (dedicated entry for each logical bank)
Automatic DRAM initialization sequence or software-controlled initialization sequence
Automatic DRAM data initialization
Data from
Data from
CSB
Features
SDRAM
is a high-level block diagram of the DDR memory controller with its associated interfaces.
master
master
ports (no direct x4 support)
master
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Figure 9-1. DDR Memory Controller Simplified Block Diagram
Address
Decode
contains detailed figures of the controller.
Open
Table
Row
FIFO
SDRAM
Control
Delay chain
Address
SDRAM
Control
Control
Control
Clock
EN
EN
Freescale Semiconductor
DDR SDRAM
Memory Array
DDR SDRAM
Memory Control
Data Qualifiers
Data Signals
Clocks
MCS[0:1]
MODT[0:1]
MA[14:0]
MBA[2:0]
MCAS
MRAS
MWE
MDM[0:3]
MCKE
MDQS[0:3]
MDQ[0:31]
MCK
MCK