MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 40
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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xl
System General Purpose Register High (SGPRH) ............................................................... 5-17
System Part and Revision ID Register (SPRIDR) ................................................................ 5-18
System Priority Configuration Register (SPCR) .................................................................. 5-19
System I/O Configuration Register Low (SICRL) ............................................................... 5-21
System I/O Configuration Register High (SICRH) .............................................................. 5-24
DDR Control Driver Register (DDRCDR) ........................................................................... 5-27
DDR Debug Status Register (DDRDSR).............................................................................. 5-28
Software Watchdog Timer High-Level Block Diagram ....................................................... 5-29
System Watchdog Control Register (SWCRR)..................................................................... 5-31
System Watchdog Count Register (SWCNR)....................................................................... 5-32
System Watchdog Service Register (SWSRR) ..................................................................... 5-32
Software Watchdog Timer Service State Diagram................................................................ 5-33
Software Watchdog Timer Functional Block Diagram......................................................... 5-34
Real Time Clock Module High Level Block Diagram ......................................................... 5-36
Real Time Counter Control Register (RTCNR).................................................................... 5-37
Real Time Counter Load Register (RTLDR) ........................................................................ 5-38
Real Time Counter Prescale Register (RTPSR).................................................................... 5-39
Real Time Counter Register (RTCTR).................................................................................. 5-39
Real Time Counter Event Register (RTEVR) ....................................................................... 5-40
Real Time Counter Alarm Register (RTALR) ...................................................................... 5-40
Real Time Clock Module Functional Block Diagram .......................................................... 5-41
Periodic Interval Timer High Level Block Diagram............................................................. 5-43
Periodic Interval Timer Control Register (PTCNR) ............................................................. 5-44
Periodic Interval Timer Load Register (PTLDR).................................................................. 5-45
Periodic Interval Timer Prescale Register (PTPSR) ............................................................. 5-46
Periodic Interval Timer Counter Register (PTCTR) ............................................................. 5-46
Periodic Interval Timer Event Register (PTEVR)................................................................. 5-47
Periodic Interval Timer Functional Block Diagram.............................................................. 5-47
Global Timers Block Diagram .............................................................................................. 5-49
Global Timers Configuration Register 1 (GTCFR1)............................................................. 5-54
Global Timers Configuration Register 2 (GTCFR2)............................................................. 5-55
Global Timers Mode Registers (GTMDR1–GTMDR4)........................................................ 5-57
Global Timers Reference Registers (GTRFR1–GTRFR4).................................................... 5-58
Global Timers Capture Registers (GTCPR1–GTCPR4) ....................................................... 5-58
Global Timers Counter Registers (GTCNR1—GTCNR4).................................................... 5-59
Global Timers Event Registers (GTEVR1—GTEVR4)........................................................ 5-59
Global Timers Prescale Registers (GTPSR1–GTPSR4)........................................................ 5-60
Timers Non-Cascaded Mode Block Diagram ....................................................................... 5-62
Timer Pair-Cascaded Mode Block Diagram ......................................................................... 5-63
Timers Super-Cascaded Mode Block Diagram..................................................................... 5-63
Power Management Controller Configuration Register ....................................................... 5-66
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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