MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 443

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

9.6
System software must configure the DDR memory controller, using a memory polling algorithm at system
start-up, to correctly map the size of each bank in memory. Then, the DDR memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank depths.
System software must also configure the DDR memory controller at system start-up to appropriately
multiplex the row and column address bits for each bank. Refer to row-address configuration in
Section 9.4.1.2, “Chip Select Configuration (CSn_CONFIG).”
these configuration bits.
At system reset, initialization software (boot code) must set up the programmable parameters in the
memory interface configuration registers. See
descriptions of the configuration registers. These parameters are shown in
Freescale Semiconductor
DDR_SDRAM_CFG_2
DDR_SDRAM_MODE
DDR_SDRAM_CFG
TIMING_CFG_3
TIMING_CFG_0
TIMING_CFG_1
TIMING_CFG_2
CS n _CONFIG
CS n _BNDS
Initialization/Application Information
Name
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Table 9-34. Memory Interface Configuration Register Initialization Parameters
Chip select memory bounds
Chip select configuration
Extended timing parameters for
fields in TIMING_CFG_1
Timing configuration
Timing configuration
Timing configuration
Control configuration
Control configuration
Mode configuration
Description
Section 9.4.1, “Register Descriptions,”
ODT_WR_CFG
ODT_RD_CFG
SDRAM_TYPE
RD_TO_PRE
PRETOACT
ACTTOPRE
ACTTORW
DYN_PWR
DQS_CFG
ODT_CFG
CS_ n _EN
AP_ n _EN
ADD_LAT
WR_LAT
CASLAT
RD_EN
32_BE
SREN
WWT
8_BE
RWT
WRT
DBW
CPO
RRT
Address multiplexing occurs according to
EXT_REFREC
ESDMODE
Parameter
SDMODE
SA n
EA n
Table
ROW_BITS_CS_ n
WR_DATA_DELAY
COL_BITS_CS_ n
BA_BITS_CS_ n
BA_INTLV_CTL
PRE_PD_EXIT
ODT_PD_EXIT
ACT_PD_EXIT
FOUR_ACT
ACTTOACT
MRS_CYC
WRTORD
CKE_PLS
NUM_PR
REFREC
WRREC
x32_EN
2T_EN
D_INIT
NCAP
9-34.
HSE
BI
for more detailed
DDR Memory Controller
Section/Page
9.4.1.2/9-10
9.4.1.3/9-11
9.4.1.4/9-12
9.4.1.5/9-14
9.4.1.6/9-16
9.4.1.7/9-18
9.4.1.8/9-21
9.4.1.9/9-22
9.4.1.1/9-9
9-49