MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 45
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Figure
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10-70
10-71
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10-80
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13-3
13-4
Freescale Semiconductor
Non-Multiplexed Address and Data Buses ......................................................................... 10-89
Local Bus Peripheral Hierarchy for High Bus Speeds........................................................ 10-90
GPCM Address Timings ..................................................................................................... 10-90
GPCM Data Timings........................................................................................................... 10-91
Interface to Different Port-Size Devices ............................................................................. 10-92
Single-Beat Read Access to FPM DRAM .......................................................................... 10-98
Single-Beat Write Access to FPM DRAM ......................................................................... 10-99
Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown)............................ 10-100
Refresh Cycle (CBR) to FPM DRAM .............................................................................. 10-101
Exception Cycle ................................................................................................................ 10-102
Interface to ZBT SRAM ................................................................................................... 10-103
I/O Sequencer Block Diagram .............................................................................................. 11-1
PCI Outbound Translation Address Registers (POTARn) .................................................... 11-3
PCI Outbound Base Address Registers (POBARn).............................................................. 11-3
PCI Outbound Comparison Mask Registers (POCMRn) ..................................................... 11-4
Power Management Control Register (PMCR) .................................................................... 11-5
Discard Timer Control Register (DTCR).............................................................................. 11-6
Outbound PCI Memory Address Translation ....................................................................... 11-8
DMA/Messaging Unit Block Diagram ................................................................................. 12-1
Outbound Message Interrupt Status Register (OMISR) ....................................................... 12-3
Outbound Message Interrupt Mask Register (OMIMR)....................................................... 12-4
Inbound Message Registers (IMR0, IMR1).......................................................................... 12-5
Outbound Message Registers (OMR0–OMR1) .................................................................... 12-5
Outbound Doorbell Register (ODR) ..................................................................................... 12-6
Inbound Doorbell Register (IDR) ......................................................................................... 12-7
Inbound Message Interrupt Status Register (IMISR)............................................................ 12-7
Inbound Message Interrupt Mask Register (IMIMR) ........................................................... 12-8
DMA Mode Register (DMAMRn) ....................................................................................... 12-9
DMA Status Register (DMASRn) ...................................................................................... 12-11
DMA Current Descriptor Address Register (DMACDARn).............................................. 12-12
DMA Source Address Register (DMASARn) .................................................................... 12-13
DMA Destination Address Register (DMADARn) ............................................................ 12-13
DMA Byte Count Register (DMABCRn)........................................................................... 12-14
DMA Next Descriptor Address Register (DMANDARn) .................................................. 12-14
DMA General Status Register (DMAGSR)........................................................................ 12-15
DMA Controller Block Diagram ........................................................................................ 12-16
DMA Chain of Segment Descriptors .................................................................................. 12-19
PCI Controller Block Diagram ............................................................................................. 13-2
PCI Interface External Signals.............................................................................................. 13-5
PCI_CONFIG_ADDRESS Register ................................................................................... 13-13
PCI_CONFIG_DATA ......................................................................................................... 13-15
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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