MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 482

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

1
Enhanced Local Bus Controller
10.3.1.17 Flash Mode Register (FMR)
The local bus Flash mode register (FMR), shown in
Table 10-24
10-34
Offset 0x0_50E0
Reset 0
Bit R (field BOOT) is set if power-on-reset configuration selects FCM as the boot ROM target.
16–19 CWTO Command wait time-out. For FCM commands that wait on LFRB being sampled high (CW0, CW1,
21–22
W
0–15
R
Bits
20
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Name
BOOT Flash auto-boot load mode. During system boot from NAND Flash EEPROM, this bit remains set to
describes FMR fields.
—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
RBW and RSW), FCM pauses execution of the instruction sequence until either LFRB is sampled high,
or a timer controlled by CTO expires, whichever occurs first. The time-out in the latter case is:
0000 256 cycles of LCLK
0001 512 cycles of LCLK
0010 1024 cycles of LCLK
0011 2048 cycles of LCLK
0100 4096 cycles of LCLK
0101 8192 cycles of LCLK
0110 16,384 cycles of LCLK
0111 32,768 cycles of LCLK
1000 65,536 cycles of LCLK
1001 131,072 cycles of LCLK
1010 262,144 cycles of LCLK
1011 524,288 cycles of LCLK
1100 1,048,576 cycles of LCLK
1101 2,097,152 cycles of LCLK
1110 4,194,304 cycles of LCLK
1111 8,388,608 cycles of LCLK
alter the use of the FCM buffer RAM. Software should clear BOOT once FCM is to be restored to
normal operation. Setting BOOT without auto-boot in progress only alters the mapping of the buffer
RAM.
0 FCM is operating in normal functional mode, with an 8 Kbyte FCM buffer RAM.
1 eLBC has been configured—either from reset or by a special operation OP = 01—to auto-load a
Reserved
4-Kbyte boot block into the FCM buffer RAM, which maps only the 4 Kbytes of NAND flash main
data region comprising the boot block. Any access to the buffer RAM is delayed until the entire boot
block has been loaded.
—
Table 10-24. FMR Field Descriptions
Figure 10-21. Flash Mode Register
15 16
0
Figure
CWTO
0
Description
0
10-21, controls global operation of the FCM.
19
0
BOOT
R
20
1
21 22
0
—
0
ECCM
23
0
24 25 26 27 28 29 30 31
0
—
Freescale Semiconductor
0
0
Access: Read/Write
AL
0
0
—
0
0
OP
0