MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 57
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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Table
Number
5-36
5-37
5-38
5-39
5-40
5-41
5-42
5-43
5-44
5-45
5-46
5-47
5-48
5-49
5-50
5-51
5-52
5-53
5-54
5-55
5-56
5-57
5-58
5-59
5-60
5-61
5-62
5-63
5-64
5-65
5-66
5-67
5-68
5-69
5-70
5-71
5-72
5-73
5-74
5-75
6-1
Freescale Semiconductor
RTC Signal Properties........................................................................................................... 5-36
RTC External Signal—Detailed Signal Description ............................................................. 5-37
RTC Register Address Map .................................................................................................. 5-37
RTCNR Bit Settings.............................................................................................................. 5-38
RTLDR Bit Settings .............................................................................................................. 5-38
RTPSR Bit Settings ............................................................................................................... 5-39
RTCTR Bit Settings .............................................................................................................. 5-39
RTEVR Bit Settings .............................................................................................................. 5-40
RTALR Bit Settings .............................................................................................................. 5-40
PIT Signal Properties ............................................................................................................ 5-43
PIT External Signal—Detailed Signal Descriptions ............................................................. 5-44
PIT Register Address Map.................................................................................................... 5-44
PTCNR Bit Settings .............................................................................................................. 5-45
PTLDR Bit Settings .............................................................................................................. 5-45
PTPSR Bit Settings ............................................................................................................... 5-46
PTCTR Bit Settings............................................................................................................... 5-46
PTEVR Bit Settings .............................................................................................................. 5-47
GTM Signal Properties.......................................................................................................... 5-51
GTM External Signals—Detailed Signal Descriptions......................................................... 5-52
GTM Register Address Map ................................................................................................. 5-53
GTCFR1 Bit Settings ............................................................................................................ 5-54
GTCFR2 Bit Settings ............................................................................................................ 5-56
GTMDR Bit Settings............................................................................................................. 5-57
GTRFR Bit Settings .............................................................................................................. 5-58
GTCPRn Bit Settings ............................................................................................................ 5-59
GTCNR Bit Settings.............................................................................................................. 5-59
GTEVRn Bit Settings ............................................................................................................ 5-60
GTPSRn Bit Settings............................................................................................................. 5-60
System Control Signals—Detailed Signal Descriptions ....................................................... 5-65
Power Management Controller Registers Memory Map ...................................................... 5-65
PMCCR Bit Settings ............................................................................................................. 5-66
PMCER Bit Settings ............................................................................................................. 5-67
PMCMR Bit Settings ............................................................................................................ 5-69
PMCCR1 Bit Settings ........................................................................................................... 5-70
PMCCR2 Bit Settings ........................................................................................................... 5-72
PCI Defined Power Management State Support ................................................................... 5-74
PCI Bus Power Management State Support.......................................................................... 5-75
Software-Controller Power-Down States—Basic Description ............................................. 5-76
MPC8313E Agent Mode Wake-Up Support......................................................................... 5-80
MPC8313E Host Mode Wake-Up Support ........................................................................... 5-82
Arbiter Register Map .............................................................................................................. 6-2
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
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