MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 712

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

Security Engine (SEC) 2.2
Table 14-39
(ISR), and interrupt clear register (ICR).
14.6.4.3
The interrupt status register (ISR) contains fields representing all possible sources of interrupts. The
interrupt status register is cleared either by a reset, or by writing the appropriate bits active in the interrupt
clear register (ICR).
are described in
14-70
I
Multiple
16–19,
24–29,
32–53,
56–57,
20–23
30–31
60–61
0–14,
Bits
15
Table 14-39. Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers
Err and Dn bits
Err and Dn bits
for execution
units (AESU,
describes the register field names in the interrupt mask register (IMR), interrupt status register
and so on.)
for channel
Interrupt Status Register (ISR)
Overflow
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Names
Done
ITO
—
Table
Figure 14-43
14-39.
Internal time out
0 No internal time out
1 An internal time out was detected
Note: Internal time out is an indication that the channel or EU has failed to respond to a slave read
Done overflow (one bit for each channel)
0 No done overflow
1 Done overflow error. Indicates that more than 15 done interrupts were queued from the channel
Err
0 No error detected
1 Error detected. Indicates that channel status register must be read to determine exact cause of
Dn
0 Not DONE
1 DONE bit indicates that the interrupting channel has completed its operation.
Err
0 No error detected.
1 Error detected. Indicates that execution unit status register must be read to determine exact
Dn
0 Not DONE.
1 DONE bit indicates that the interrupting EU has completed its operation.
Reserved, set to zero.
without an interrupt clear from the host.
the error.
cause of the error.
or write within 16 cycles, which would only occur in an impending hang condition. Assertion
of this interrupt indicates the SEC controller has completed the transaction to avoid a hang,
however the ‘completed’ transaction does not result in a successful read or write, and the
interrupt advises the system that the slave transaction was unsuccessful.
shows the bit positions of each potential interrupt source. The bit fields
Description
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