MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 218

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

System Configuration
5.2.4.5
The PCI local access window n base address registers (PCILAWBAR0–PCILAWBAR1) are shown in
Figure
Table 5-11
5.2.4.5.1
The core may use a PCI peripheral device to fetch its boot vector. For this purpose, the
PCILAWBAR0[BASE_ADDR] reset value is set according to the value set in the reset configuration word
high BMS field.
Table 5-12
5-10
20–31
0–19
‘
Bits
Offset 0x60
Reset
Figure 5-6. PCI Local Access Window n Base Address Registers (PCILAWBAR0–PCILAWBAR1)
W
R
5-6.
BASE_ADDR Identifies the 20 most-significant address bits of the base of local access window n . The specified
0x68
1
0
The reset value of PCILAWBAR0[BASE_ADDR] depends on the reset configuration word high values. See
Section 5.2.4.5.1, “PCILAWBAR0[BASE_ADDR] Reset Value,”
defines the bit fields of PCILAWBAR0–PCILAWBAR1.
defines the reset value of PCILAWBAR0[BASE_ADDR].
Name
—
PCI Local Access Window n Base Address Register
(PCILAWBAR0–PCILAWBAR1)
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
PCILAWBAR0[BASE_ADDR] Reset Value
base address should be aligned to the window size, as defined by PCILAWAR n [SIZE].
Reserved. Write has no effect, read returns 0.
Table 5-11. PCILAWBAR0–PCILAWBAR1 Bit Settings
Table 5-12. PCILAWBAR0[BASE_ADDR] Reset Value
RCWHR[BMS]
BASE_ADDR
0
1
PCILAWBAR0[BASE_ADDR]
All zeros
Reset Value
Description
0xFF800
0x00000
1
for a detailed description.
19 20
Freescale Semiconductor
—
Access: Read/Write
31