MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 831

• Manufacturer Part Number: MPC8313ECZQADDC
• Description: Microprocessors - MPU 8313 REV2.2 PB ENC EXT
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313ECZQADDC

• Processor Series: MPC8313E
• Core: e300
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 133 MHz
• Program Memory Size: 16 KB
• Data Ram Size: 16 KB
• Interface Type: I2C
• Mounting Style: SMD/SMT
• Package / Case: PBGA
• Number Of Programmable I/os: 32
• Number Of Timers: 4

coalescing that may be specified in TXIC/RXIC. Software may poll this register at any time to check for
pending interrupts. If an event occurs and its corresponding enable bit is set in the event mask register
(TEMASK), the event also causes a hardware interrupt at the PIC. A bit in the timer event register is
cleared by writing a 1 to that bit position. Figure 15-4 describes the definition for the TMR_TEVENT
register.
Table 15-110
Freescale Semiconductor
16–23
8–13
Bits
0–6
Offset eTSEC1:0x2_4E04
Reset
Reset
14
15
24
25
6
7
W
W
R
R
16
0
Name
ALM2
ALM1
ETS2
ETS1
PP1
PP2
describes the fields of the TMR_TEVENT register fields for the timer.
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—
—
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
Reserved
External trigger 2 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
External trigger 1 timestamp sampled
0 external trigger timestamp not sampled
1 external trigger timestamp sampled
Reserved
Current time equaled alarm time register 2
0 alarm time has not be reached yet
1 alarm time has been reached
Current time equaled alarm time register 1
0 alarm time has not be reached yet
1 alarm time has been reached
Reserved
Indicates that a periodic pulse has been generated based on FIPER1 register.
0 periodic pulse not generated
1 periodic pulse generated
Indicates that a periodic pulse has been generated based on FIPER2 register.
0 periodic pulse not generated
1 periodic pulse generated
Table 15-110. TMR_TEVENT Register Field Descriptions
—
Figure 15-106. TMR_TEVENT Register Definition
—
5
ETS2
6
All zeros
All zeros
ETS1
23
7
Description
PP1
24
8
PP2 PP3
25
Enhanced Three-Speed Ethernet Controllers
26
—
27
13
—
ALM2 ALM1
Access: W1C
14
15
31
15-113