MPC8313ECZQADDC Freescale Semiconductor, MPC8313ECZQADDC Datasheet - Page 129
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MPC8313ECZQADDC
Manufacturer Part Number
MPC8313ECZQADDC
Description
Microprocessors - MPU 8313 REV2.2 PB ENC EXT
Manufacturer
Freescale Semiconductor
Datasheet
1.MPC8313CZQADDC.pdf
(1214 pages)
Specifications of MPC8313ECZQADDC
Processor Series
MPC8313E
Core
e300
Data Bus Width
16 bit
Maximum Clock Frequency
133 MHz
Program Memory Size
16 KB
Data Ram Size
16 KB
Interface Type
I2C
Mounting Style
SMD/SMT
Package / Case
PBGA
Number Of Programmable I/os
32
Number Of Timers
4
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0x2_48A0–
0x2_4B00–
0x2_4744–
0x2_4820–
0x2_47FC
0x2_4AFC
0x2_472C
0x2_473C
0x2_480C
0x2_481C
0x2_487C
0x2_488C
0x2_489C
0x2_4BF4
0x2_4BF8
0x2_4728
0x2_4730
0x2_4734
0x2_4738
0x2_4740
0x2_4800
0x2_4804
0x2_4808
0x2_4810
0x2_4814
0x2_4818
0x2_4880
0x2_4884
0x2_4888
0x2_4890
0x2_4894
0x2_4898
Offset
TUND—Transmit undersize frame counter
TFRG—Transmit fragments frame counter
CAR1—Carry register one register
CAR2—Carry register two register
CAM1—Carry register one mask register
CAM2—Carry register two mask register
RREJ*—Receive filer rejected packet counter
Reserved
IGADDR0—Individual/group address register 0
IGADDR1—Individual/group address register 1
IGADDR2—Individual/group address register 2
IGADDR3—Individual/group address register 3
IGADDR4—Individual/group address register 4
IGADDR5—Individual/group address register 5
IGADDR6—Individual/group address register 6
IGADDR7—Individual/group address register 7
Reserved
GADDR0—Group address register 0
GADDR1—Group address register 1
GADDR2—Group address register 2
GADDR3—Group address register 3
GADDR4—Group address register 4
GADDR5—Group address register 5
GADDR6—Group address register 6
GADDR7—Group address register 7
Reserved
Reserved
ATTR—Attribute register
MPC8313E PowerQUICC™ II Pro Integrated Processor Family Reference Manual, Rev. 2
eTSEC Counter Control and TOE Statistics Registers
Register
Table 2-2. Memory Map (continued)
eTSEC DMA Attribute Registers
14
Hash Function Registers
14
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
—
R
R
0xFE03_FFFF
0x000F_FFFD
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
—
—
15.5.3.6.42/15-100
15.5.3.6.43/15-100
15.5.3.6.44/15-101
15.5.3.6.45/15-102
15.5.3.6.46/15-103
15.5.3.6.47/15-105
15.5.3.6.48/15-106
15.5.3.7.1/15-107
15.5.3.7.2/15-107
15.5.3.8.1/15-108
Section/Page
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Memory Map
2-25
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